Timing vernier using a delay locked loop

ABSTRACT

A method for synchronizing a plurality of programmable timing verniers with a reference pulse signal, each of the verniers being programmable to one of a plurality of timing steps within a delay range determined by a control signal applied to a bias input. A first and second control vernier is selected from the plurality of verniers, the first control vernier is programmed to a first delay, and the second control vernier is programmed to a second delay. The first and second control verniers are triggered together to generate respective first and second delay signals. A difference pulse signal is generated with a duty cycle corresponding to a difference between the generated first delay signal and second delay signal. The duty cycle of the pulse signal is compared to a duty cycle of the reference pulse signal to generate a difference signal pulse. The difference signal pulse is coupled to the bias input of the verniers to adjust the delay range, such that the duty cycle of the difference signal approaches the duty cycle of the reference pulse signal.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.12/687,541, filed on Jan. 14, 2010, which is a continuation of U.S.application Ser. No. 12/144,186, (now issued as U.S. Pat. No. 7,671,650)filed on Jun. 23, 2008, which is a continuation of U.S. application Ser.No. 11/550,245 (now issued as U.S. Pat. No. 7,391,247), filed on Oct.17, 2006, which is a divisional of U.S. application Ser. No. 11/205,082(now issued as U.S. Pat. No. 7,129,760), filed Aug. 17, 2005, which is acontinuation of U.S. application Ser. No. 11/037,365 (now issued as U.S.Pat. No. 7,038,517), filed Jan. 19, 2005, which is a continuation ofU.S. application Ser. No. 10/402,130 (now issued as U.S. Pat. No.6,853,231), filed Mar. 31, 2003, which is incorporated herein byreference in its entirety.

FIELD OF THE INVENTION

The present invention relates to a system and method for generatingtiming signals, and more particularly to delay locked loop (DLL)controlled timing vernier (delay generator) for generating such timingsignals.

BACKGROUND OF THE INVENTION

The generation of timing signals with fine resolution time delays findsimportant application in Automated Test Equipment (ATE) that is used fortesting integrated circuit devices, where precise timing edge placementis required. A typical test requires that data from a Device Under Test(DUT) must be compared with expected data at a precisely controlled timeand for a precisely controlled period. For example a tester might expecta signal on a data pin of the DUT to be low 2.435 ns after receipt of atrigger signal for a time period of 500 ps.

Typical ATEs use a timing vernier (essentially a delay generator) togenerate these fine timing resolution signals from a precisely generatedfixed frequency global clock signal. The timing vernier is essentially adelay generator capable of generating very small phase shifts, usuallyin the order of picoseconds, of the global clock signal. Timing verniersare useful because the available timing resolution is determined by thedifference between two precisely controlled propagation delay values, itis not constrained by minimum gate propagation delay.

Commercially available timing vernier devices are typically programmablevia an eight bit code and can be retriggered at frequencies in the orderof several hundred MHZ. The minimum resolution timing step of thevernier is determined by its minimum delay range divided by 255 (for an8-bit code). However any number of bits (e.g. 16) may be used tosubdivide the delay range. The delay range of the vernier is usuallyexternally adjustable within its minimum delay range and maximum delayrange (dynamic range), by a current reference signal or a bias voltagesignal.

Generally several timing verniers are used to divide the period of theglobal clock signal into several time slots. In typical ATE's the fixedfrequency global clock signal is sent to all timing verniers from whichall signal generation and sampling are measured. A disadvantage of afixed frequency system is that the time slots are fixed relative to theperiod of the global clock signal.

Modern ATE's are required to test a wide variety of devices and thusthere is a need for testers to operate over a wider frequency range inorder to test this variety of devices.

Previous ATEs approached the problem of variable tester clockfrequencies by computing the difference or remainder in delay betweenedges of the fixed global clock signal and the variable test clocksignal and to compensate for this difference by using calibratedverniers. When the sum of the remainders is greater than one clockcycle, an additional clock cycle is inserted into the variable testclock signal. This requires complex control logic and is difficult tooperate reliably.

A further problem is that because multiple timing verniers are used togenerate tester clock frequencies process variations and temperaturevariations cause the vernier delays to drift and limits theirresolution. This problem is particularly exacerbated by varying thefrequency of the global clock signal.

Accordingly there is need for a timing vernier that may be locked to avariable frequency clock and that is minimally susceptible to processand operating condition variations.

Furthermore there is a need for a method for synchronizing multipleverniers to accommodate a variable frequency clock and to also reducesusceptibility to fluctuations in supply voltages.

SUMMARY OF THE INVENTION

In accordance with a general aspect of the invention there is provided amethod for synchronizing a plurality of programmable timing vernierswith a reference signal, each vernier being programmable to one of aplurality of timing steps within a delay range and the delay range beingdetermined by a control signal applied to a bias input, the methodcomprising the steps of: (a) providing a first and second controlvernier; (b) programming the first control vernier to a first delay; (c)programming the second control vernier to a second delay; (d) triggeringthe first and second control verniers together to generate respectivefirst and second delay signals; (e) generating a first difference signalcorresponding to a difference between the generated first delay signaland second delay signal; and (f) comparing the first difference signalto a reference signal to generate a second difference signal, the seconddifference signal being coupled to the bias input of the verniers toadjust the delay range.

In an embodiment the first difference signal is a pulse and the secondreference signal is also a pulse.

In accordance with one aspect of this invention there is provided amethod for synchronizing a plurality of programmable timing vernierswith a reference pulse signal, each of the verniers being programmableto one of a plurality of timing steps within a delay range and the delayrange being determined by a control signal applied to a bias input, themethod comprising the steps of: (a) selecting a first and second controlvernier from the plurality of verniers; (b) programming the firstcontrol vernier to a first delay; (c) programming the second controlvernier to a second delay; (d) triggering the first and second controlverniers together to generate respective first and second delay signals;(e) generating a difference pulse signal having a duty cyclecorresponding to a difference between the generated first delay signaland second delay signal; (f) comparing the duty cycle of the pulsesignal to a duty cycle of the reference pulse signal to generate adifference signal pulse, the difference signal being coupled to the biasinput of the verniers to adjust the delay range such that the duty cycleof the difference signal approaches the duty cycle of the referencepulse signal.

In accordance with another aspect of this invention there is provided asystem for synchronizing a plurality of programmable timing vernierswith a reference pulse signal, each vernier being programmable to one ofa plurality of timing steps within a delay range and the delay rangebeing determined by a control signal applied to a bias input, the systemcomprising: (a) first and second control verniers selected from theplurality of verniers, and being programmed to respective first delayand second delays; (b) a pulse generator for generating a differencepulse signal having a duty cycle corresponding to a difference between agenerated first delay signal and second delay signal; (c) a duty cycledetector for comparing the duty cycle of the pulse signal to a dutycycle of the reference pulse signal to generate a difference signalpulse; and (d) a feed back circuit for coupling the difference signalback to the bias inputs of the verniers to adjust the delay range suchthat the duty cycle of the difference signal approaches the duty cycleof the reference pulse signal.

In an embodiment the duty cycle detector compares the duty cycle of apulse generated from the difference between the vernier minimum delayand the vernier maximum delay and a pulse that is one clock cycle long.The duty cycle detector generates a bias voltage, which is fed back tothe timing verniers. This bias voltage controls the delay through thetiming vernier.

In a still further embodiment the control signals are distributed to theverniers as current signals.

In a still further embodiment the timing verniers are arranged in groupswith each group having a local current to voltage conversion circuit.

In a still further embodiment the groups include local calibration.

Since verniers may be used to divide a clock period into a predefinednumber of segments. As the clock frequency changes the bias voltage isadjusted to keep the correct number of predefined segments.

An advantage of the present invention is the ability to synchronizemultiple verniers to a variable frequency clock signal.

Another advantage of the present invention is that multiple timingverniers may be synchronized while minimizing their dependence onvariable operating conditions such as temperature and processvariations.

Another advantage of the present invention is that the delay range ofthe programmable timing verniers can be locked to a variable frequencyclock, which is particularly useful in ATE's.

Other aspects and features of the present invention will become apparentto those ordinarily skilled in the art upon review of the followingdescription of specific embodiments of the invention in conjunction withthe accompanying figures.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present invention will now be described, by way ofexample only, with reference to the attached Figures, wherein:

FIG. 1 is a schematic block diagram of a timing vernier control systemaccording to an embodiment of the present invention;

FIG. 2 is a block diagram of a programmable timing vernier according toan embodiment of the present invention;

FIG. 3 is a circuit diagram of a delay segment according to anembodiment of the present invention;

FIG. 4 is a circuit diagram of a pulse generator according to anembodiment of the present invention;

FIG. 5 is a timing diagram;

FIG. 6 is a circuit diagram of functional blocks shown in FIG. 1;

FIG. 7 is a schematic diagram of showing a further embodiment of thepresent invention;

FIG. 8 is a circuit diagram of a duty cycle detector and charge pumpcircuit according to the second embodiment of the invention;

FIG. 9 is a circuit diagram of an analog processing circuit;

FIG. 10 is a circuit diagram of current to voltage converter accordingto the present invention;

FIG. 11 is a circuit diagram of a variable delay circuit; and

FIG. 12 is a timing diagram showing operation of the circuit in FIG. 7.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth toprovide a thorough understanding of the invention. However, it isunderstood that the invention may be practiced without these specificdetails. In other instances, well-known structures circuits or and/orprocesses have not been described or shown in detail in order not toobscure the invention. In the description and drawings, like numeralsrefer to like structures or processes.

Referring now to FIG. 1 there is shown a timing vernier system 100 inaccordance with an embodiment of the invention. The system 100 includesa delay locked loop (DLL) 102 for providing a delay compensated controlsignal to a plurality of programmable timing verniers 170 on asemiconductor device. Each vernier 170 receives a global clock signalCLK and the control signal, which is a filtered bias voltage VBVRN 191for setting its delay range. Each timing vernier 170 may be programmedto one of 256 within the delay range by an 8-bit code applied to avernier programming circuit 180. The vernier programming circuit 180receives the global clock CLK and the 8-bit code on a vernier data businput. The programming circuit 180 includes registers and a decoder inorder to generate the appropriate programming signals to the vernier170, these circuits are well known in the art, and will not be discussedfurther. In summary, the total delay across each vernier is controlledby the bias voltage VBVRN applied to the vernier and the number of stepsprogrammed into the programming control.

A delay line for the delay locked loop circuit 102 is comprised of twocontrol verniers 120 and 130 which are duplicates of the timing verniers170. The clock signals to these control verniers are derived from apulse generator 110. The global clock signal is fed to the pulsegenerator 110. The pulse generator produces a delay signal PDEL and areference signal PREF as shown in FIG. 5. The signal PREF is a positivepulse of one clock cycle in duration and which is generated every fourcycles of the clock signal CLK. The PDEL signal is simply the clocksignal CLK divided by four. The PDEL signal is coupled to the clockinput of each control vernier 120 and 130. Control timing vernier 120 isprogrammed to the verniers minimum range delay and produces an outputpulse signal DMIN. The control timing vernier 130 is programmed with thefull range delay of the verniers and produces output pulse signal DMAX.The pulse DMIN occurs first as it has the minimum delay path and iscoupled to a set input of an SR Flip-Flop 140 causing the output DP ofthe flip-flop to go high. The pulse DMAX occurs after pulse DMIN and iscoupled to the reset input of the SR Flip-Flop causing the output DP ofthe flip-flop to go low. Thus the output DP of the flip-flop generates apulse signal that corresponds to the difference in the delay between theminimum delay vernier 120 and the maximum delay vernier 130. Thus thelength of the DP pulse corresponds to the delay span or range of thetiming verniers.

The output pulse DP from the SR flip-flop is coupled to a duty cycledetector 150 which compares the duration of the DP pulse with the PREFpulse. The DP and the PREF pulses are preferably non overlapping. Theoutput of the duty cycle detector 150 drives a charge pump 160, which inturn generates a voltage VBIAS, which is fed back to the control vernier120 and 130. The DP pulse causes VBIAS to move in one direction and thenthe PREF causes it to move in the other direction. Thus voltage VBIAShas a voltage ripple.

A bias voltage filter 190 having a large time constant is used to removethe voltage ripple from the signal VBIAS and generate the vernier biasvoltage signal VBVRN 191 which is provided to the timing verniers 170.If this filter was not present the voltage ripple on VBIAS would phasemodulate the timing of the verniers 170. The Filter 190 also isolatesthe VBIAS feedback loop from the capacitive load of the timing verniers.The capacitive load of the timing verniers has the potential todestabilize the control feedback loop.

The delay locked loop will stabilize when the length of the DP pulse isthe same length as the PREF pulse. This requires that the differencebetween a maximum delay vernier and a minimum delay vernier is one clockcycle. This means that the delay range for all other verniers on thechip has been set to 1 clock cycle.

One advantage of this system is that it will compensate for temperatureand supply voltage changes, since changes in the timing verniers will bereflected in the control verniers which in turn will adjust the biascontrol of the verniers.

Another advantage is that it also permits the system to vary the clockfrequency and the verniers will automatically be readjusted to fullysubdivide the clock into a predetermined number of segments.

Referring to FIG. 2 there is shown a circuit diagram of the programmabletiming vernier 170 according to an embodiment the present invention. Adelay input DI is connected to a first of a series cascade of delaysegments 220, 230, 240, 250 via inverter 210. Each delay segment isprogrammable and has sixteen coarse programming bits D [0:15] and fourfine programming bits D [0:3] etc. The delay segments are alsoresponsive to a bias voltage VBVRN for setting their individual delayrange. A delayed version of the inverted input signal is coupled from anode 251 in the delay cascade where it is connected to inverter 270 anddelay segment 260.

The output of the inverter 270 and the delay segment 260 are coupled toinputs of a NAND gate 280, which outputs via an inverter 290 a pulsesignal DO. As may be seen the inverter 270, NAND gate 280, inverter 290and delay segment 260 form a pulse generator. The width of the outputpulse DO is determined by the delay through delay segment 260.

One advantage of using the delay segment 260 to generate the length ofthis pulse, rather than a more typical delay chain is that the width ofthe pulse will be a known fraction (up to ¼) of a clock cycle. Asdescribed above the circuit of FIG. 1 is used to set the bias voltagelevel so that the delay through a timing vernier programmed to maximumdelay (the delay mostly made up of four timing segments) is one clockcycle long. Therefore the delay through one timing segment which isprogrammed to a maximum delay will be ¼ of the clock period. If delaysegment is programmed to a mid point delay then the pulse width will be⅛ of the clock period. This pulse width programming is shown in FIG. 2by coupling the programming inputs of the delay segment 260 to theappropriate supply voltages.

As will be recognized by those skilled in the art, the circuit of FIG. 2generates a positive output pulse DO in response to a rising edge on theinput DI.

Referring to FIG. 3 there is shown a schematic diagram of the delaysegment 220 of FIG. 2, generally indicated by numerals of 300, accordingto an embodiment of the present invention. The input signal is coupledvia an input terminal IN to the gates of transistors 320 and 330, whichform an input inverter. A high voltage supply line is connected to thesource of transistor 310. When transistor 320 is on (a low voltage onits gate) current will flow from VDD to node 390. The magnitude of thiscurrent will be controlled by the bias voltage VBIAS on the gate oftransistor 310. If VBIAS is lower, then more current will flow throughthe transistor.

The transistors 320 and 330 output a signal onto the node 390 which isconnected to capacitors 360 383 and the gates of transistors 340 and345. Transistors 340 and 345 form inverter 350. Each of the capacitors360 383 is controlled by its respective transistor 370 387 form aprogrammable capacitive element. If a signal DC applied to the gate ofthe transistor 370 is high then the full capacitance C of capacitor 360is connected between the node 390 and ground. If the signal DC is low,then transistor 370 is off. Node 390 sees a series capacitance ofcapacitor 360 and the parasitic drain capacitance (Cf) of transistor 370between itself and ground. The value of that capacitance is C*Cf/(C+Cf).Additionally, node 390 has a parasitic capacitance Ccn 391.

The coarse programming bits are each connected to a programmable elementwith a capacitor of size C. The fine programming signals are connectedto programmable elements with capacitor sizes of C/4 and parasiticcapacitance of Cf/4 as transistors 384 to 387 are preferably ¼ the sizeof transistors 370 to 373. The capacitors are preferably Metal InsulatorMetal or MIM capacitors rather than MOS type capacitors.

The operation of the delay segment may be explained as follows. When thesignal applied to the input terminal IN is low, transistor 320 is turnedon. This permits current to flow from VDD to node 390. The bias voltage(VBIAS) on the gate of transistor 310 determines this current. Thiscurrent charges the node 390 and its connected capacitance. As thecurrent charges the capacitance the voltage on node 390 begins to rise.The amount of time it takes to charge is proportional to the capacitanceand inversely proportional to the current. If there are more capacitorsconnected, it takes longer. When the voltage on node 390 reaches theswitching point of inverter 350 the output is driven low. When the inputsignal is high transistor 320 is off and transistor 330 is on. Thecharge on node 390 flows to ground and the voltage on node 390 falls.When the switching point of inverter 350 is reached the output goeshigh. Transistor 330 is sized so that it can quickly discharge the node390.

In one embodiment, each delay element may be programmed to one ofsixty-four possible delays. The programming sequence is one fine bit,two fine bits, three fine bits, one course bit, one course and one finebit, and so on up to 16 course bits. The capacitors are physicallypositioned in arrays of four wide. The fourth unused fine bit is presentfor physical symmetry. The importance of maintaining physical symmetryin precision capacitance arrays is well known to those skilled in theart. The additional bit may also be used in testing. The four delaysegments therefore have a total of 256 different programmable delays.

In another embodiment of the timing vernier the four fine programmingbits are slightly different. One will be configured to have C/4−20%, oneC/4, one C/4+20% and one C/4+40%. The programming sequence will beslightly different. During calibration, it will be determined which ofthe 4 different fine bits is optimally used to provide monotonicity inthe delay. The programming sequence will be the selected fine bit fromblock 220, the selected fine bits from block 220 and 230, the selectedfine bits from blocks 220, 230 and 240, a course bit from any block, theaforementioned course bit plus the selected fine bit from block 220 andso on up to all 64 course bits.

In order to subdivide the clock into 256 equal segments, 255 divisionpoints must be inserted into the clock period. Thus programming a 0 willresult in a pulse that is coincident with the rising edge of the clock.Programming a 1 (one fine bit) will result in a pulse that occurs 1/256of a clock period after the rising edge of the clock. Programming a 3(three fine bits) will result in a pulse that occurs 3/256 of a clockperiod after the rising edge of the clock. Programming a 4 (one coursebit) will result in a pulse that occurs 4/256 of a clock period afterthe rising edge of the clock. Programming a value of 255 (63 coarse bitsand 3 fine bits) will result in a pulse that occurs 255/256 of a clockperiod after the rising edge of the clock. Programming all of the 64coarse bits will give a pulse that occurs exactly 1 clock period afterthe rising edge of the clock (in other words coincides with the nextrising edge of the clock). This is the full range of programming and isused to program the maximum delay line shown in FIG. 1 (130).

Referring to FIG. 4 there is shown a schematic diagram of the pulsegenerator 110. This pulse generator results in the PREF pulse and the DPpulse in every four clock cycles, as shown in FIG. 5. It is assumed thatpulses PREF and DP are non-overlapping.

Referring to FIG. 6 there is shown a schematic diagram of preferredembodiments of the SR flip-flop 140 of FIG. 1, the duty-cycle detector 1and charge-pump 660. In essence the functions of the duty cycle detectorand charge pump have been combined in a single circuit.

An enable signal is coupled via an input of a NAND gate 623 to the gateof transistor 640, which is in turn coupled between a VDD supply and anode 670. When the enable signal EN is low, the circuitry is disabledand the node 670 is pulled to ground. When the signal EN is high thecircuitry is enabled. The signal PREF is also coupled via the secondinput of the NAND gate 623 to the gate terminal of transistor 640. Whensignal PREF is high, the gate of transistor 640 will be low. This meansthat transistor 640 will be on. Charge will flow from the node VDDthrough transistor 640 and will be added to node 670. The voltage onnode 670 will rise. When signal PREF is low, transistor 640 will be offand no charge will flow from VDD to node 670.

The SR flip-flop is a well known circuit formed by a pair ofcross-coupled NAND gates 611, 613 and respective inverters 610, 612. Theoutput of the flip-flop DP is coupled to the gate of a transistor 650coupled between the node 670 and ground. When signal DMIN goes high theSR latch will set signal DP high. This will put a high on the gate oftransistor 650, turning it on. Charge will be removed from node 670through transistor 650 to the ground node. The voltage on node 670 willfall. Later signal DMIN will return low and signal DMAX will go high.This causes signal DP to go low which will turn off transistor 650.

Transistors 640 and 650 are sized such that the same amount of currentflows when they are turned on. That is if both transistors 640 and 650were on at the same time then the amount of charge being added to node670 through transistor 640 would be the same as the amount removed fromnode 670 by transistor 650. Those skilled in the art will recognize thattransistor 640 is typically 2.5× to 3× larger than transistor 650 tobalance the charging and discharging currents.

Resistors 661 and 662 and capacitors 663, 664, 665 and 666 form asmoothing filter. The voltage on node 670 will see sudden decreases andincreases in voltage as transistors 640 and 650 add and remove charge.The smoothing filter reduces the effect of this voltage change andvoltage node VBIAS will preferably have a 60 mV ripple or smaller. Thefilter responds relatively quickly so as not to create instability inthe loop.

Bias filter 190 (FIG. 1) is of similar construction to filter 660.However the component values are different. Filter 190 has a slowerresponse and removes the ripple from VBIAS.

If the DP signal is high for longer than the PREF signal, transistor 650will be on for longer than transistor 640. More charge will be removedfrom node 670 by transistor 650 than is added by transistor 640. Theaverage voltage on node 670 will decrease. This lower average voltagewill be reflected in the Vbias. The lower Vbias will increase thecurrent through transistor 310 (FIG. 5), which will result in a shorterdelay through the delay segments. The DMAX signal will be earlier andthe DP pulse will be shorter.

Conversely if signal PREF is high for longer than signal DP, transistor640 will be on for longer time than transistor 650 and this will occurduring each fourth clock period. More charge will be added to node 670by transistor 640 than is removed by transistor 650. The average voltageon node 670 will rise. This higher average voltage will be reflected inthe Vbias. The higher Vbias will decrease the current through transistor310, which will result in a longer delay through the delay segments. TheDMAX signal will be delayed and the DP pulse will be longer.

The circuit of FIG. 6 compares the duty cycle of the DP pulse to that ofthe PREF pulse and then adjusts the Vbias until the DP and the PREFpulses have the same length.

Referring to FIG. 7 there is shown a schematic diagram of anotherembodiment of the invention. This embodiment is less susceptible topower supply fluctuations than the embodiment shown in FIG. 1. As shown,circuit blocks 110, 120, 130, 140, 170 and 180 are the same as for thecorresponding blocks in FIG. 1 and bear the same numeric reference.However the duty cycle detector and the charge pump are combined inBlock 710. An output voltage signal Vbias from the block 710 is providedto an analog processing block 120 which generates the voltage signalVBFB and the current signals IBV[0:N−1].

In addition each vernier 170 receives its clocking from a vernier timerblock 175. The verniers 170 and their corresponding vernier programmingcircuit 180 are grouped in blocks of four. Each group of four verniershas a local current to voltage converter with local calibration circuit730 to produce a local vernier bias voltage VBVRN.

It is a well-known phenomenon that the supply voltage on an integratedcircuit can vary. This variation is due in part to the resistance of thepower supply buses and the current flowing through the bus. The externalpower supply may also vary. The supply voltages may vary by as much as10% across the chip. In the circuit shown in FIG. 1, a variation in thesupply voltages in the timing verniers can result in a variation in thecurrent supplied through transistor 310 (FIG. 3) in the variousverniers. This will lead to slightly different delays. In a precisiontiming system these variations are undesirable.

The circuit of FIG. 7 includes a current to voltage converter 730 forconverting reference current distributed to the local blocks of verniersinto the bias voltage VBVRN. The local current to voltage converter willset up a local vernier bias voltage that compensates for any variationin the supply voltage. A local calibration is also provided in block 730to compensate for other local factors.

FIG. 8 is a schematic diagram of the duty cycle detector and charge pump710 of FIG. 7. The charge pump is similar to that of shown in FIG. 6except that the polarity of the charge pump has been reversed and someof the schematic chains implemented differently. Gates 810, 811, 812,813 and 814 form a SR latch that corresponds to block 140 shown in FIG.7. When the DP pulse is high then transistor 640 is on and charge isadded to node 670. When signal PREF is high, then transistor 650 is onand charge is removed from node 670. Signal PREF transits 4 gates 820,821, 822 and 823 prior to activating transistor 650. Transmission gate814 is inserted in the DMIN path (gates 810, 814, 811 and 830) so thatit also has 4 gate delays prior to activating transistor 640. Thistechnique of inserting transmission gates to equalize the delay throughdifferent paths is well known in the art.

FIG. 9 is a schematic diagram of the analog processing circuit 720 shownin FIG. 7. The bias voltage Vbias is compared to a reference voltageVref by differential amplifier 910. The output of the differentialamplifier drives a gate of a transistor 911. The reference voltage Vrefis preferably equal to VDD/2 and locally generated. If Vbias is greaterthan Vref then the output of the 910 will be low. This will turn ontransistor 911 and allow current source 920 connected to itssource-drain circuit to add its current to a node 912 in addition to thecurrent supplied by current source 930. If Vbias is less than Vref theoutput of the differential amplifier 910 will be high and transistor 911will be off. Only the current from current source 930 will be added tonode 912. Current source 920 is configured to deliver 16 μA and 930 isconfigured to deliver 8 μA. Thus either 8 μA or 24 μA is supplied tonode 912. This current flows through transistor 940 and is mirrored intransistors 941 and 942 and 943. The voltage on node VBFB will thereforeeither be one of two levels. The first level will be that which issufficient for 8 μA to flow through transistor 943 and the other will bethat which is sufficient for 24 μA to flow through transistor 943.

Signal VBFB is used as the feedback signal to close the loop. Oneskilled in the art will realize that excess filtering of the feedbacksignal will slow the response and cause potential instability. Thereforesignal VBFB is used for the feedback and the filtered VBFB is used togenerate the IBV currents.

Filter 950 is comprised of resistors 951 and 952 and capacitors 953,954, 955 and 956. It will average out the voltage variations of nodeVBFB and provide that value to the gate of 961. Transistor 961 willconduct a current between 8 μA and 24 μA. This will be mirrored by thecascaded NMOS current mirrors made by transistors 962, 963, 964 and 965.There are N current mirrors, each generating an IBV bias current. EachIBV current is connected to a group of four timing verniers.

FIG. 10 is a schematic diagram of the current to voltage converter withlocal calibration (block 730). This circuit combines the vernier biascurrent IBV with a coarse adjustment and a fine adjustment circuit. Node1040 is a current summing node and it combines the bias current with thecoarse and fine adjustment circuits.

Current IBV is mirrored by the current mirror formed by transistors 1001and 1002. Transistor 1002 is preferably four times (4×) larger thantransistor 1001. This has the effect of adding 4×IBV to node 1040. Thecurrent is increased by a factor of four and then later decreased by afactor of four. This allows the current summing to occur at easilycontrollable levels. Very small currents are difficult to reliablygenerate.

The coarse adjustment circuit (1020) consists of eight pairs of PMOStransistors. One such pair consists of series connected transistors 1021and 1022. Device 1021 has its gate connected to a locally generated biasvoltage VB3. Transistor 1022 has its gate connected to coarseprogramming signal CC0. If signal CC0 is low then transistor 1022 is on,and a current defined by the bias voltage VB3 is added to node 1040.Similarly devices 1023 and 1024 form a pair as do devices 1025 and 1026.Three such pairs are shown but there are preferably eight pairscontrolled by signals CC[7:0]. Other embodiments may have more or fewerpairs. The coarse adjustment circuit is preferably only used in testing.

The fine adjustment circuits comprise 256 pairs of transistors 1031 and1032 and transistors 1033 to 1038. Similar to the coarse adjustmentcircuit the 256 pairs of transistors combine a current onto node 1039.This current is mirrored by current mirror 1034/1038. The range of thefine adjustment circuits is approximately equal to a coarse step.Transistor 1038 is preferably 1/9 the size of transistor 1034 so thecurrent flowing through transistor 1038 is 1/9 that of transistor 1034.Current mirror 1035/1036 is also a 1:9 ratio so that the current addedto node 1040 is 1/81 that of node 1039. Negative offset block 1050subtracts a small amount of current from node 1040. The negative offsetcircuit preferably subtracts ½ the current of a coarse programming bit.The fine adjustment circuit compensates for this and requires a midrange setting (128 of 256 bits). This permits the current to be trimmedboth + and − from the nominal.

The summed currents of node 1040 are mirrored by current mirror1005/1006. Device 1006 is preferably ¼ the size of 1005. This returnsthe current levels to that of the original current IBV.

Transistor 1008 converts the current to a bias voltage, which isfiltered by filter 1010 prior to distribution to the 4 local timingverniers.

Bias generating circuit 1060 generates local bias voltages 1061 and 1062from bias voltage VBDAC.

Someone skilled in the art will realize that there are a number ofelements not shown in FIG. 10. Specifically these elements set the nodesof the circuit to a known value in a disabled state. In this disabledstate a minimum amount of power is dissipated. These elements areomitted for clarity.

Returning to FIG. 7, the vernier timer circuit 175 has been added tocontrol the timing pulses of the timing vernier and its programmingblock. It is conceivable that the vernier could be programmed to maximumdelay on one clock and minimum delay on the next. This would result incontention as the pulses would overlap and the programming changes wouldnot have time to be implemented. Block 175 restricts the vernier to 1pulse every two clock cycles. A circuit suitable for implementing thisfunction is shown in FIG. 11. A variable delay circuit in FIG. 11 iscomprised of two delay segments of the type shown in FIG. 2. Theyreceive the bias voltage VBVRN of the local verniers. The programming isset through metal mask options. The shaded area on FIG. 12 shows theprogramming range of this variable delay. The data for the next vernierprogramming is latched on the rising edge of signal CL.

FIG. 12 shows the timing operation of this circuit. Also shown on FIG.12 is the Vernier Output signal. The first pulse is a pulse programmedto a value 0 and the second is programmed to a value of 255.

In the preceding description, for purposes of explanation, numerousdetails are set forth in order to provide a thorough understanding ofthe embodiments of the invention. However, it will be apparent to oneskilled in the art that these specific details are not required in orderto practice the invention. In other instances, well-known electricalstructures and circuits are shown in block diagram form in order not toobscure the invention. For example, specific details are not provided asto whether the embodiments of the invention described herein areimplemented as a software routine, hardware circuit, firmware, or acombination thereof.

The above-described embodiments of the invention are intended to beexamples only. Alterations, modifications and variations can be effectedto the particular embodiments by those of skill in the art withoutdeparting from the scope of the invention, which is defined solely bythe claims appended hereto.

1. An apparatus comprising: first delay circuitry configured to delay an input signal by a first duration and a second duration concurrently where the first duration and the second duration are adjustable by a first control signal, to provide a pulsed signal having a duration corresponding to a difference between the first duration and the second duration; a comparator configured to compare the duration of the pulsed signal to a reference pulse signal duration to produce a comparison output signal, in response to the comparison output signal, the delay circuitry changing the duration of the pulsed signal to substantially correspond to the reference pulse signal duration; and second delay circuitry configured to delay the input signal to provide a delayed input signal in response to a second control signal, the first control signal and the second control signal electrically corresponding to each other.
 2. A method for producing a timing signal, comprising: delaying an input signal by a first duration and a second duration concurrently where the first duration and the second duration are adjustable by a first control signal, to provide a pulsed signal having a duration corresponding to a difference between the first duration and the second duration; comparing the duration of the pulsed signal to a reference pulse signal duration to produce a comparison output signal, in response to the comparison output signal, the delay circuitry changing the duration of the pulsed signal to substantially correspond to the reference pulse signal duration; and delaying the input signal to provide a delayed input signal in response to a second control signal, the first control signal and the second control signal electrically corresponding to each other.
 3. A timing system comprising: a pulse generator for providing a pulsed signal having an adjustable pulse duration, the adjustable pulse duration being associated with a delayed version of an input signal and being adjustable by a first control signal; a comparator for comparing the adjustable pulse duration and a reference pulse signal duration and for adjusting the first control signal to change the adjustable pulse duration to substantially correspond to the reference pulse signal duration; and timing circuitry for delaying the input signal to provide a delayed input signal in response to an electrically corresponding version of the first control signal. 